The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, device drive current improvement becomes more important. Among efforts being made to improve device drive current, forming a strained silicon channel, thus enhancing carrier mobility, is a known practice. Strain, sometimes referred to as stress, can enhance bulk electron and hole mobility. The performance of a MOS device can be enhanced through a strained-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon is placed under strain, the electron mobility is dramatically increased. One way to develop strain is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has inherent strain. Since the lattice constant of SiGe is larger than that of silicon, the silicon film is under biaxial tension and thus the carriers exhibit strain-enhanced mobility.
Strain can also be induced by forming a strained contact etch stop (CES) layer on a MOS device. When a contact etch stop layer is deposited, due to the lattice spacing mismatch between the CES layer and the underlying layer, an in-plane strain develops to match the lattice spacing. In the channel region, strain also develops as a response to the strain applied, and the carrier mobility is enhanced. Strain applied to the channel region is determined by the intrinsic strain in the CES layer and its thickness, and the intrinsic strain generally increases when the thickness of the CES layer increases.
While CES layers are desirable for strain engineering, very thick CES layers cause difficulty in subsequent processes, such as inter-layer dielectric (ILD) gap filling, and therefore are undesired in high-density circuit design. FIG. 1 illustrates a conventional method of improving strain without the necessity of increasing the thickness of the CES layer. After the formation of the spacers 4, an extra recess step is performed on the substrate 2 along edges of the respective spacers 4, forming recesses 6 in the source/drain regions 12. A strained CES layer 10 is then formed. Due to the recesses 6, strain applied on the channel region 8 by the CES layer 10 increases, and about a seven percent device drive current improvement has been observed due to the increased strain.
The drive current improvement is significant in large devices. In small devices, particularly devices manufactured using 65 nm technologies and beyond, the drive current improvement is less observable, even though the channel mobility is improved. A possible reason is that the recessing of the source/drain regions 12 causes current crowding effects in regions 16, which are substantially narrower portions of the source/drain regions 12, and the device drive current is degraded accordingly. The current crowding effects are especially severe in small devices. In devices manufactured using 90 nm technology, the device drive current degradation due to current crowding effects is less than about one percent. In devices manufactured using 65 nm technology, the device drive current is degraded about 12 percent. With the further scaling of the devices, the device drive currents are expected to degrade even more.
What is needed, therefore, is a method to increase the strain applied to the channel region while eliminating the detrimental current crowding effects, so that device drive currents are improved.